Product Summary

The XCF08PVOG48C is a In-System Programmable Configuration PROM. Available in 1 to 32 Mb densities, the XCF08PVOG48C provides an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The XCF08PVOG48C includes 32 Mb, 16 Mb, and 8 Mb PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes.

Parametrics

XCF08PVOG48C absolute maximum ratings: (1)Internal supply voltage relative to GND:-0.5V to +2.7V; (2)I/O supply voltage relative to GND:-0.5V to +4.0V; (3)JTAG I/O supply voltage relative to GND:-0.5V to +4.0V; (4)Input voltage with respect to GND: -0.5V to +3.6V; (5)Voltage applied to High-Z output:-0.5V to +3.6V; (6)Storage temperature (ambient):-65℃ to +150℃; (7)Junction temperature:+125℃.

Features

XCF08PVOG48C features: (1)In-System Programmable PROMs for Configuration of Xilinx FPGAs; (2)Low-Power Advanced CMOS NOR Flash Process; (3)Endurance of 20,000 Program/Erase Cycles; (4)Operation over Full Industrial Temperature Range(–40℃ to +85℃); (5)IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing; (6)JTAG Command Initiation of Standard FPGA Configuration; (7)Cascadable for Storing Longer or Multiple Bitstreams; (8)Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ); (9)I/O Pins Compatible with Voltage Levels Ranging From 1.8V to 3.3V; (10)Design Support Using the Xilinx ISE Alliance and Foundation Software Packages; (11)1.8V Supply Voltage; (12)Serial or Parallel FPGA Configuration Interface; (13)Available in Small-Footprint VO48, VOG48, FS48, and FSG48 Packages; (14)Design Revision Technology Enables Storing and Accessing Multiple Design Revisions for Configuration; (15)Built-In Data Decompressor Compatible with Xilinx Advanced Compression Technology.

Diagrams

XCF08PVOG48C block diagram

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XCF08PVOG48C
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